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@article{198578,
        author = {B.SWAPNA and P. SAI PRANEETH and P.UJWAL and P.MANIDHAR REDDY and P.AKHILA REDDY},
        title = {DESIGN AND SIMULATION OF POWER EFFICIENT FIR FILTER WITH SHIFT-ADD BASED RTL MODELING AND OPTIMIZATION},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {10586-10590},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=198578},
        abstract = {This paper presents the design and simulation of a power efficient Finite Impulse Response (FIR) filter using a shift-add based Register Transfer Level (RTL) modeling optimization. Conventional FIR filters rely on multiplier-based architectures, which result in high power consumption and increased hardware complexi-ty. To overcome these limitations, the proposed design replaces multipliers with shift and add operations, thereby reducing area and improving power efficiency. The FIR filter is modeled using Verilog HDL and im-plemented using FPGA design tools such as Xilinx Vi-vado.},
        keywords = {FIR Filter, Shift-Add Technique, RTL Modeling, Low Power Design, FPGA Implementation.},
        month = {April},
        }