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@article{198746,
        author = {Dr. A. Vikas and M. Nikhitha and M. Harshini and M. Saadhwik and M. Srivathsav},
        title = {Design and Simulation of CMOS Low Dropout Regulator for Low Power Applications Using Cadence},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {10684-10691},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=198746},
        abstract = {Portable biomedical instruments, IoT nodes, and mixed-signal subsystems need a supply that is both quiet and dependable, even when the available headroom is small. That requirement keeps low-dropout regulators relevant in spite of the efficiency advantage of switching converters. This work presents the design and simulation of a CMOS LDO regulator implemented in Cadence Virtuoso using the 90 nm process environment described in the source report. The regulator uses a PMOS pass device, a telescopic cascode error amplifier, a resistive feedback network, and a compensated closed loop intended for low-power operation. The circuit is evaluated through DC, AC, and transient simulations. The reported operating-point result gives an output voltage of 1.499 V, while the quiescent current is 68 µA. The measured line and load regulation are about 1.499 mV/V and 1.489 mV/mA, respectively. During load transients, the output shows roughly 18 mV undershoot and 22 mV overshoot. The summarized results also report a dropout voltage of about 300 mV, which indicates that regulation is maintained with modest headroom, although the dropout target remains the main area for improvement. The design is well suited to low-noise, low-power integrated supplies.},
        keywords = {CMOS LDO, low-dropout regulator, Cadence Virtuoso, low-power design, line regulation, load regulation, transient response},
        month = {April},
        }