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@article{198796,
        author = {Mr. M. Gnanesh Goud and M. Vaishnavi and M. Manga and P. Deepak Reddy and P. Pavan},
        title = {ASIC Implementation of FFT Processor},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {11896-11899},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=198796},
        abstract = {This project implements an 8-point Fast Fourier Transform (FFT) processor using ASIC design. In Stage-1, the design is developed in Verilog/VHDL using a radix-2 DIT architecture and verified through simulation. In Stage-2, it is synthesized and implemented through ASIC backend processes like placement, routing, and timing analysis. The final design achieves efficient performance, low area, and low power, making it suitable for real-time DSP applications.},
        keywords = {RTL Modelling, Backend Implementation},
        month = {April},
        }