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@article{199522,
        author = {M Sai Krishna and Bai Harikumar and Gajula Varun Satya and Gaddam Rajashekar and Golla Hari Prasad and Gudepu Vamshi Goud},
        title = {IMPLEMENTATION OF MIPS 8-BIT SINGLE CYCLE Processor USING VERILOG HD},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {13942-13947},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=199522},
        abstract = {This research presents the design and implementation of an 8-bit single-cycle MIPS processor using Verilog HDL. The primary objective is to develop a simplified processor architecture that enables clear understanding of instruction execution within a single clock cycle. The system integrates essential components such as Program Counter, Instruction Memory, Register File, Arithmetic Logic Unit, Data Memory, and Control Unit. Each instruction undergoes sequential stages including fetch, decode, execute, memory access, and write-back within one cycle, ensuring structural simplicity. Unlike conventional 32-bit processors, the proposed 8-bit design minimizes hardware complexity while retaining core architectural principles. The processor supports arithmetic, logical, memory, and control flow operations, making it suitable for educational and FPGA-based applications. Simulation results validate correct functionality of instruction execution and control signal behavior. This work provides a practical platform for understanding processor design fundamentals and serves as a foundation for future enhancements such as pipelining and performance optimization.},
        keywords = {MIPS Processor, Verilog HDL, Single Cycle Architecture, FPGA Design, 8-bit Processor, RISC Architecture.},
        month = {April},
        }