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@article{205004,
        author = {Sanjana S and T. Swetha and L. Lakshmi Prathima and B. Bhagyasri and M.Daizy Pujitha and N.Lakshmi Manogna},
        title = {Design and Verification of Dual Port RAM on FPGA Using Xilinx Vivado},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {1},
        pages = {5152-5161},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=205004},
        abstract = {This paper presents the complete design, simulation, synthesis, and on-board hardware verification of a True Dual Port RAM (TDPRAM) targeting the Nexys A7 Artix-7 FPGA development board, implemented using Xilinx Vivado 2024.1. The proposed design provides  two  fully  independent,  synchronous  read/write  ports  (Port  A  and  Port  B),  each with its own clock domain, reset, enable, write-enable, 8-bit address bus, and 32-bit data bus,  sharing a common 256-location×32-bit memory array. The design is described in Verilog HDL, structurally verified through RTL schematic analysis, functionally validated via behavioral simulation, and finally tested on live FPGA hardware using the Xilinx Vir- tual Input/Output (VIO) debug core. The complete RTL-to-hardware design flow is docu- mented, including resource utilization, timing closure, and VIO probe measurements.  Re- sults confirm simultaneous, conflict-free dual-port operation suitable for high-throughput SoC and embedded processing applications.},
        keywords = {Dual Port RAM, True Dual Port RAM, FPGA, BRAM, Vivado, VIO, Verilog HDL, Nexys A7, RTL Schematic, Simulation, Synthesis, Digital Memory Design.},
        month = {June},
        }