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@article{205478,
        author = {Keval and Dr Sharanbasappa Shetkar},
        title = {Design & Simulation of I2C Master Slave Communication protocol using Verilog HDL},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {1},
        pages = {6855-6858},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=205478},
        abstract = {The Inter-Integrated Circuit protocol widely known as I²C protocol is being used in serial communication protocol for connecting digital devices using two lines: SDA and SCL. This research designs and simulates an I²C Master-Slave communication system using Verilog HDL. The master system used to indicate communication and as it also controls data transfer, while the slave responds to commands and exchanges data. This design implements key I²C features such as START/STOP conditions, address transmission, read/write operations, and ACK/NACK signaling. The system is designed at the Register Transfer Level (RTL) for accurate control and timing representation. A Verilog testbench has been developed to verify communication functionality and protocol compliance. Simulations are performed making use of ModelSim and Xilinx Vivado to analyze timing and waveform behavior. Hence the results demonstrate reliable data transfer and correct implementation of the I²C protocol.},
        keywords = {I²C, Master-Slave communication system, SDA and SCL, Register Transfer Level (RTL), ModelSim},
        month = {June},
        }