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@article{207906,
        author = {Firadosh C D and Santhosha B G and Amulya A H and Deepika.S and Harshita.P.K},
        title = {Design of energy efficient full adder and ripple carry adder architecture by using cadence virtuoso},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {3},
        pages = {3270-3273},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=207906},
        abstract = {This project presents the design and analysis of an energy-efficient Full Adder (FA) and Ripple Carry Adder (RCA) architecture using 45 nm CMOS technology in Cadence Virtuoso. The objective is to minimize power consumption, delay, and power-delay product (PDP) while maintaining reliable circuit performance for VLSI applications. The full adder cell is designed using optimized transistor-level logic techniques to reduce switching activity and leakage power. The proposed FA is further cascaded to construct the ripple carry adder architecture for multi-bit arithmetic operations. Simulation and schematic implementation are carried out in the Cadence Virtuoso environment, and performance parameters such as average power dissipation, propagation delay, and energy efficiency are evaluated under different input conditions. Results demonstrate that the 45 nm design achieves significant reduction in power consumption and improved speed compared to conventional CMOS adder structures. The proposed architecture is suitable for low-power digital signal processing and portable electronic applications requiring high computational efficiency with reduced silicon area.},
        keywords = {Full Adder, Ripple Carry Adder (RCA), Cadence Virtuoso, Low Power VLSI, Power-Delay Product (PDP), Transmission Gate Logic, CMOS Digital Integrated Circuits, Spectre Simulation.},
        month = {August},
        }