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@article{208130,
        author = {E Manasa and Arpitha K and Anjali B G and Divyashree K Y},
        title = {Design of digital counter by using 90nm technology using cadence tool.},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {4},
        pages = {467-471},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=208130},
        abstract = {This paper introduces a novel, power-optimized architecture for 3-bit and 4-bit synchronous binary up-counters utilizing predictive clock-gating and look-ahead carry logic. Traditional synchronous counter topologies suffer from redundant dynamic power consumption caused by continuous clock toggling across higher-order flip-flops. By integrating state-aware activation logic, the proposed design selectively gates clock signals to inactive stages while preserving single-cycle state transitions for MOD-8 and MOD-16 sequences. Analytical modeling and gate-level logic reduction demonstrate a significant reduction in dynamic power dissipation with zero performance penalty on the critical path (f_{max}). This framework provides an energy-efficient sequential logic building block targeted for ultra-low-power microcontrollers and portable IoT hardware units.},
        keywords = {Synchronous Up-Counter, Predictive Clock-Gating, Low-Power VLSI, Dynamic Power Reduction, Look-Ahead Carry Logic, MOD-8 / MOD-16 Counters, Sequential Logic Optimization.},
        month = {September},
        }