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@article{208171,
        author = {Priyanka M and Sahana M A and Suhana M and Varsha N and Mr Santhosh B G},
        title = {Design and Simulation of a 4:1 Multiplexer in Cadence tool},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {4},
        pages = {800-804},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=208171},
        abstract = {With the rapid growth of portable and high-performance electronic systems, the demand for low-power and area-efficient VLSI circuits has increased significantly. Multiplexers are fundamental combinational logic components widely used in digital systems for data selection and signal routing. This work presents in the design and simulation of a 4:1 Multiplexer using CAD tools. The proposed design is implemented at the transistor level using CMOS logic tool to achieve reduced power consumption, compact area utilization, and improved switching performance. The schematic design is developed in cadence and subsequently verified through layout generation and simulation in Microwind. Performance parameters such as power dissipation, propagation delay, and transistor count are analyzed to evaluate the efficiency of the design. The simulation results demonstrate that the CMOS-based 4:1 multiplexer provides reliable operation with lower power requirements, making its suitable for modern VLSI and digital integrated circuit applications.},
        keywords = {},
        month = {September},
        }