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@article{208360,
        author = {Mr. Akash Ananda Mendke and Sukhdev K Thorat and Manojkumar Vilas Kukade and Dr. Kailash Baliram Sapnar},
        title = {FPGA-Based Emulation of Quantum Computing Systems: A Survey of Architectures, Noise Modelling, And Digital Twin Approaches},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {no},
        pages = {21-25},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=208360},
        abstract = {Classical simulation of quantum circuits is fundamentally constrained by the exponential growth of state-vector memory and computation with qubit count, motivating a long-running effort to accelerate quantum-circuit emulation using reconfigurable hardware. Field-programmable gate arrays (FPGAs) offer fine-grained parallelism, deterministic timing, and reprogrammability, making them an attractive substrate for such emulation. A substantial body of work spanning nearly two decades has explored architectures for mapping quantum gate operations onto FPGA fabric. This survey traces that evolution, from early circuit-model emulators through serial-parallel and high-precision architectures to recent iteration-scheduling optimisations that improve energy efficiency relative to CPU and GPU baselines. It then examines a parallel and largely separate thread of research on noise and decoherence modelling, where calibration-driven “digital twins” of physical qubit devices have been constructed primarily in software, using device-specific parameters extracted from hardware calibration data rather than generic noise assumptions. We argue that the convergence of these two threads — real-time-capable FPGA emulation architectures and calibration-driven noise models — remains largely unexplored, and we outline this convergence as a concrete research gap: a hardware-native, real-time noise-adaptive digital twin of a quantum processor. Beyond consolidating scattered literature from VLSI, reconfigurable-computing, and quantum-information venues into a single narrative, this survey is written to directly motivate and ground an ongoing low-cost FPGA-based prototyping effort, positioning it within the broader trajectory of the field. The survey concludes with a discussion of open challenges, including standardised fidelity metrics, scalability beyond small qubit counts, integration with cryogenic control electronics, and hybrid quantum-classical algorithm testbeds, each identified as a concrete direction for future hardware-native digital-twin research.},
        keywords = {FPGA, quantum computing emulation, quantum circuit simulation, decoherence modelling, digital twin, noise-adaptive hardware, reconfigurable computing},
        month = {September},
        }