Assessment of Power Optimization Using VLSI Techniques
Akula Rajitha
optimization, VLSI, physical design, layout, placement, routing, MED, BDD, CMOS
With the advancement in compact, portable and high-density micro-electronic devices and systems, the power dissipated in very large scale integrated (VLSI) design circuits has become a critical concern. Accuracy and efficiency in power estimation involved in the design phase is important in order to meet power specifications without high cost redesign process. This paper, presents a review of the power optimization theory approach and the estimation techniques of recent proposition. VLSI design has fascinating application area for all combination circuit optimization. In virtual context all classical combination optimization issues, occur in natural way as subtasks. The rapid technological advancement and major theoretical concept advances the mathematics of VLSI design, which has changed significantly over the last two decades. This survey paper also gives a recent account on the key factors in optimization design. And presents a survey of layout techniques in order to design low power digital CMOS circuits. It describes the problems faced by the designers at the physical design abstraction and reviews some of the techniques which are proposed to overcome these difficulties.
Article Details
Unique Paper ID: 145102

Publication Volume & Issue: Volume 4, Issue 7

Page(s): 281 - 286
Article Preview & Download

Go To Issue

Call For Paper

Volume 5 Issue 4

Last Date 25 September 2018

About Us enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on

Social Media

Contact Details

Telephone:704 821 9842/43