LOW POWER AND AREA EFFICIENT SYSTEM WITH ONE-CYCLE CORRECTION OF TIMING ERRORS IN PIPELINES WITH STANDARD CLOCKED ELEMENTS
Author(s):
Peddi venkatesh, S.Saidarao
ISSN:
2349-6002
Cite This Article:
LOW POWER AND AREA EFFICIENT SYSTEM WITH ONE-CYCLE CORRECTION OF TIMING ERRORS IN PIPELINES WITH STANDARD CLOCKED ELEMENTSInternational Journal of Innovative Research in Technology(www.ijirt.org) ,ISSN: 2349-6002 ,Volume 6 ,Issue 3 ,Page(s):79-83 ,July 2019 ,Available :IJIRT148543_PAPER.pdf
Keywords:
Low power, Breadth efficient, Timing error, Flip-Flop, Timing Speculation
Abstract
Compelling abatement of timing edges, alleged timing hypothesis, is a applied address for abbreviation voltage for a activity ambit and thusly its adeptness use. Regardless, anticipation of timing blow increases with the voltage ascent and thusly, the goofs have to be adapted with little aeon discipline. Here present an added Razor access by barter cast bend by exhausted bolt, which makes added cutting than others. The proposed action is a low-power and breadth advantageous framework with expedient misstep antidote utilizing little aeon discipline. The commune and ability acceptance are lessened by utilizing this approach. This framework handles the masterminding affair amid exhausted locks application altered non-cover surrendered exhausted alarm developments rather than the accepted individual exhausted alarm flag. So utilizes a yielded cloc alarm generator. Which gives abbreviate put off banderole to snares.
Article Details
Unique Paper ID: 148543

Publication Volume & Issue: Volume 6, Issue 3

Page(s): 79 - 83
Article Preview & Download




Go To Issue



Call For Paper

Volume 6 Issue 7

Last Date 25 December 2019


About Us

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org

Social Media

Google Verified Reviews

Contact Details

Telephone:8200 61 5067
Email: editor@ijirt.org
Website: ijirt.org

Policies