HDL IMPLEMENTATION OF 8-BIT SIGNED CALCULATOR ON SEVEN SEGMENT

HDL IMPLEMENTATION OF 8-BIT SIGNED CALCULATOR ON SEVEN SEGMENT
Author(s):
Abhishek Tyagi, Raveesh Chauhan, Utkarsh Verma, Farah Naz
Keywords:
Signed Calculator, Schematics, Verilog, FPGA, EDA Tool
Abstract
In whole, this design performs following arithmetic operations: 8-bit binary addition, subtraction, multiplication and division. All these operations are performed by combining different modules such as Adder, Subtractor, Multiplier and Divider using sub modules in which basic gates were used. This calculator performs required operation of positive as well as negative numbers. Digital Circuit of these combinational circuits were firstly designed on the Schematic Sheet on EDA (Electronic Design Automation) tool then Verilog codes of all those circuits were successfully written. The result of simulation was attained with successful execution of Verilog Hardware Description Language (VHDL) which was performed using XILINX ISE Design Suite 14.7. Afterwards the Design is being Implemented on FPGA board, FPGA board accepts the input from user and gives output as led’s off(0) and on(1) respective to the final output of calculator.
Article Details
Unique Paper ID: 152439 Publication Volume & Issue: Volume 8, Issue 3 Page(s): 423 - 429
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