Design and Implementation of VLSI DHT highly Modular and Parallel Architecture for Image Compression

Farheen Maryam; Naela Husna

Design and Implementation of VLSI DHT highly Modular and Parallel Architecture for Image Compression

Authors: Farheen Maryam, Naela Husna

Unique Paper ID: 144121
Volume: 3
Issue: 6
PageNo: 148-152

Keywords: Discrete Hartley Transform (DHT) DHT domain processing image compression Xilinx Spartan family

Abstract:
Discrete Hartley transform is one of the most imperative algorithms of the signal processing and image processing system. Now a day in each field obligatory an ever increasing demand for high speed processing and low area design. Many types of discrete Hartley transform algorithm are design in different adder but bit by bit is required high speed adder.In addition, the hardware complexity can be expressively condensed using sub expression sharing technique of the proposed algorithm in highly parallel VLSI implementation. With efficient sharing of multipliers having the same constant and using the advantages of the proposed algorithm, the numbers of multipliers and adders used has been significantly reduced and is kept at a minimum compared with that of the existing algorithms. Efficient implementation of multipliers with a constant is possible in VLSI. Digital image processing is the use of computer algorithms to perform image processing on digital images.In this project, image compression has been taken as an application to prove the functionality of DHT algorithm in the field of digital signal processing.

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Cite This Article

ISSN: 2349-6002
Volume: 3
Issue: 6
PageNo: 148-152

Design and Implementation of VLSI DHT highly Modular and Parallel Architecture for Image Compression

Available:https://ijirt.org/Article?manuscript=144121

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