Implementationof High-Performance Double-Gate SOI Circuit Design

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ISSN: 2349-6002 ESTD Year: 2014

UGC approved journal no 47859

Implementationof High-Performance Double-Gate SOI Circuit Design
Author(s):
Bukya Balaji
Keywords:
Circuit design, CMOS, double-gate SOI, high-performance, low-power.
Abstract
Double-gate fully-depleted (DGFD) SOI circuits are viewed as the next generation VLSI circuits. This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuitdesign for low power and high performance.This paper presents the design of a45nm FD-DG SOI MOSFET and studies the impact of versionof channel doping and gate oxide thickness (TOX) on numeroustool parameters. Characteristics for the proposed MOSFEThave been obtained by way of considering most useful values of channeldoping and TOX. Cogenda’s Visual TCAD device has been used forthe device simulation and parameter extraction.
Article Details
Unique Paper ID: 144472 Publication Volume & Issue: Volume 1, Issue 7 Page(s): 680 - 683
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