A Study of Globally Shared-Medium On-Chip Interconnect
Author(s):
Bukya Balaji
Keywords:
IC design, RC/RLC Interconnection, VLSI Systems.Transmission Line, On-chip Interconnect.
Abstract
Timing driven physical design, synthesis, and optimization tools necessity efficient closed-form delay models for assessing the delay associated with each net in an integrated circuit (IC) design.In this paper, we display that with straightforward optimizations, the traffic among different cores can be reservedrelatively low. This in turn permits simple shared-mediuminterconnects to be built using communication circuitsdriving transmission lines. This architecture compromises extremely low latencies and can support a large number ofcores without the need for packet switching, eradicatingcostly routers.
Article Details
Unique Paper ID: 144473

Publication Volume & Issue: Volume 1, Issue 5

Page(s): 1211 - 1214
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