Optimization of Full adder cells Using HDL

J.Mallikarjunarao; P.Srinivas; S.Ramakoteswara Rao; B.Ramarao

Optimization of Full adder cells Using HDL

Authors: J.Mallikarjunarao, P.Srinivas, S.Ramakoteswara Rao, B.Ramarao

Unique Paper ID: 145256
Volume: 4
Issue: 8
PageNo: 156-160

Keywords: Adder Low power Multiplexer RCA adder

Abstract:
Power consumption has emerged as a primary design constraint for integrated circuits (ICs). In the Nanometer technology regime, leakage power has become a major component of total power [1]. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU, and the power consumption of an ALU can be lowered by lowering the power consumption of Full adder. So the full adder designs with low power characteristics are becoming more popular these days. In this paper we are going to design four different types of Full adder these are applied to 32-bit RCA .The four designs will be developed using Verilog HDL.

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Cite This Article

ISSN: 2349-6002
Volume: 4
Issue: 8
PageNo: 156-160

Optimization of Full adder cells Using HDL

Available:https://ijirt.org/Article?manuscript=145256

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Impact Factor
8.01 (Year 2024)

UGC Approved
Journal no 47859

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