DESIGN AND IMPLEMENTATION OF WALLACE TREE MULTIPLIER USING PARALLEL PREFIX ADDERS

DESIGN AND IMPLEMENTATION OF WALLACE TREE MULTIPLIER USING PARALLEL PREFIX ADDERS
Author(s):
M.Bhavani, L.Jahnavi, K.Vasanthi, K.Kavitha Rani, M.Sandhya Rani, K.Krissi Praneetha
Keywords:
Arithmetic Logic Unit (ALU), Brent Kung adder (BKA), Carry look-ahead adder (CLA), Kogge stone adder (KSA), Parallel prefix adders (PPAs), Wallace tree multiplier
Abstract
Delays have become increasingly crucial in modern VLSI technology. In order to design the circuit, an efficient ALU is required. All logical computations, such as addition and multiplication, are handled by the ALU. Multiplication is used to reduce the number of partial products while increasing the speed of the operation. An adder is the fundamental building block of every digital design. Any adder should be able to satisfy in terms of speed and area. The area (number of LUTs), delay (ns), and number of bonded IOBs of the 16-bit Wallace tree multiplier and 16-bit Parallel prefix adders (Carry look-ahead adder, Kogge stone adder, and Brent Kung adder) are compared in this project. VLSI and simulation were used to design these, and Xilinx was used to synthesis them (ISE) 14.7.
Article Details
Unique Paper ID: 155674 Publication Volume & Issue: Volume 9, Issue 1 Page(s): 1445 - 1450
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