Author Login IJIRT Partner Network (IPN) Login

DESIGN AND IMPLEMENTATION OF WALLACE TREE MULTIPLIER USING PARALLEL PREFIX ADDERS

  • Unique Paper ID: 155674
  • Volume: 9
  • Issue: 1
  • PageNo: 1445-1450
  • Abstract:
  • Delays have become increasingly crucial in modern VLSI technology. In order to design the circuit, an efficient ALU is required. All logical computations, such as addition and multiplication, are handled by the ALU. Multiplication is used to reduce the number of partial products while increasing the speed of the operation. An adder is the fundamental building block of every digital design. Any adder should be able to satisfy in terms of speed and area. The area (number of LUTs), delay (ns), and number of bonded IOBs of the 16-bit Wallace tree multiplier and 16-bit Parallel prefix adders (Carry look-ahead adder, Kogge stone adder, and Brent Kung adder) are compared in this project. VLSI and simulation were used to design these, and Xilinx was used to synthesis them (ISE) 14.7.
Download article email to a friend

Cite This Article

  • ISSN: 2349-6002
  • Volume: 9
  • Issue: 1
  • PageNo: 1445-1450

DESIGN AND IMPLEMENTATION OF WALLACE TREE MULTIPLIER USING PARALLEL PREFIX ADDERS

Related Articles

Impact Factor
8.01 (Year 2024)
UGC Approved
Journal no 47859

Join Our IPN

IJIRT Partner Network

Submit your research paper and those of your network (friends, colleagues, or peers) through your IPN account, and receive 800 INR for each paper that gets published.

Join Now

Latest Publication

Archive

View More

Recent Conferences

NCSEM 2024

National Conference on Sustainable Engineering and Management - 2024 Last Date: 15th March 2024

Submit inquiry