Turbo Coder for LTE Implementation in VLSI Using Verilog HDL
Author(s):
G. Deepa, G. Mahalakshmi
Keywords:
Turbo codes, Channel coding, Interleaver, SISO, Iterative decoder, MAP, Cadence, Xilinx Vivado.
Abstract
Turbo codes are error correction codes that are widely used in communication systems. Turbo codes exhibits high error correction capability as compared with other error correction codes. This paper proposes a Very Large Scale Integration (VLSI) architecture for the implementation of Turbo decoder. Soft-in-soft out decoders, interleaver and Deinterleaver is used in the decoder side which employs Maximum-a-Posteriori (MAP) algorithm. The number of iterations required to decode the information bits being transmitted is reduced by the use of MAP algorithm. For the encoder part, this paper uses a system which contains two Recursive convolutional encoders along with pseudorandom interleaver in encoder side. The Turbo encoding and decoding is done using Octave, Xilinx Vivado, tools. The system is implemented and synthesized in Application Specific Integrated Circuit (ASIC). This paper presents the FPGA implementation simulation results for Turbo encoder and decoder structure for 3GPP-LTE standard.
Article Details
Unique Paper ID: 156809

Publication Volume & Issue: Volume 9, Issue 5

Page(s): 48 - 55
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