Low-Power Timing-Error Control Using a Timing Error Tolerant Circuit Technique

P. Balakrishnan; S.V Ramanan

Low-Power Timing-Error Control Using a Timing Error Tolerant Circuit Technique

Authors: P. Balakrishnan, S.V Ramanan

Unique Paper ID: 159764
Volume: 9
Issue: 12
PageNo: 726-731

Keywords: Timing-Error flip-flop setup time data transition CLK time-borrowing technique

Abstract:
Real-Time operating conditions of digital integrated circuits play a key role in state-of-the-art systems. The overhead resulting from margining for worst case conditions is now a major energy contributor. In this paper a timing error tolerant circuit technique for low- power timing- error control is proposed. Controlling the transparent window of the clock enables the critical path to detect and correct the timing error-induced irregular data transition that occurs after the clock's rising edge. The timing error is directly corrected by a small amount of logic. It also introduces a time borrowing strategy, which corrects for future errors. The time-borrowing technique can be used at any site that has a quick flip-flop setup time. The timing error occurs in two stages sequentially, the arranged CLK in the second stage keeps a transparent window open long enough to allow regular data to be saved without modifying the system CLK.

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Cite This Article

ISSN: 2349-6002
Volume: 9
Issue: 12
PageNo: 726-731

Low-Power Timing-Error Control Using a Timing Error Tolerant Circuit Technique

Available:https://ijirt.org/Article?manuscript=159764

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Journal no 47859

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