IMPACT OF POWER MINIMISATION TECHNIQUES FOR TESTING LOW-POWER VLSI CIRCUIT

IMPACT OF POWER MINIMISATION TECHNIQUES FOR TESTING LOW-POWER VLSI CIRCUIT
Author(s):
Rita Aggarwal
Keywords:
Low-Power VLSI Circuits, Power Minimisation Techniques
Abstract
Power consumption in chips has grown as a side effect of technological progress. In the absence of targeted countermeasures, test-time power usage and fluctuations would be much higher. To guarantee the high quality of the final product, VLSI testing comprises the whole range of testing techniques and infrastructures that are built into a system-on-chip. The study focuses on the Impact of Power Minimisation Techniques for Testing Low Power VLSI Circuits. The study also focuses on Methods for Power Minimization in Modern VLSI Circuits. In addition, the study highlights strategies and challenges for low-power VLSI designs. Methods for testing sometimes include failure modeling and test development to ensure each device receives enough test patterns. Furthermore, the study examines Leakage Power Reduction in CMOS VLSI Circuits. Lastly, Power Minimisation Techniques for Testing Low Power VLSI Circuits are the main focus of the study.
Article Details
Unique Paper ID: 160920 Publication Volume & Issue: Volume 10, Issue 2 Page(s): 346 - 360
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