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DESIGN OF LOW POWER SRAM CELL WITH IMPROVED NOISE MARGIN USING FINFET

  • Unique Paper ID: 164726
  • Volume: 10
  • Issue: 12
  • PageNo: 2580-2584
  • Abstract:
  • This project aims to develop an SRAM cell that can achieve a high noise margin at low power consumption by using FinFETs. The conventional use of CMOS technology introduces challenges such as elevated leakage current, short channel effect (SCE), and substantial power dissipation, all of which significantly impact SRAM performance. Therefore, we propose the adoption of Gated FinFET-based SRAM cells with pass transistor feedback as an alternative to CMOS-based counterparts. This strategic shift aims to address issues associated with short-channel effects, enhance operational speed, diminish leakage, reduce power consumption, improve mobility, and facilitate efficient transistor scaling. The ultimate goal is to create faster SRAM cells operating at lower power levels with high noise margins, thereby advancing the overall performance of the SRAM system.
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Cite This Article

  • ISSN: 2349-6002
  • Volume: 10
  • Issue: 12
  • PageNo: 2580-2584

DESIGN OF LOW POWER SRAM CELL WITH IMPROVED NOISE MARGIN USING FINFET

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8.01 (Year 2024)
UGC Approved
Journal no 47859

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