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Exploring CMOS Technology for High-Speed and Efficient BCD Adder Designs

  • Unique Paper ID: 168490
  • Volume: 11
  • Issue: 5
  • PageNo: 1282-1286
  • Abstract:
  • Applications of decimal arithmetic become more significant in the domains of science and finance. Conversions from binary to decimal and from decimal to binary are necessary when doing decimal arithmetic on binary hardware. These transformations result in imprecise outcomes that cost businesses money. Consequently, decimal hardware is critically needed. The paper suggests circuits for adding decimals and shows how complementary metal-oxide semiconductor (CMOS) technology might be used to implement them. The suggested circuits are simulated and their operation is confirmed using the LTSPICE SPICE simulator program. The circuits are compared to previous efforts in the literature and simulated utilizing 45nm, 65nm, and 180nm technologies. Owing to the dearth of prior research in the field and for comparative purposes, this work was additionally designed. Fourier Transform (FFT) is an important signal processing technique widely used in various applications, such as audio and image processing, telecommunications, and scientific computing [1]. Many electronic applications require the best FFT with the least area, low power consumption, high speed. To design an FFT, a multiplier and adder are required. To perform multiplication, adder is the important block. So, if addition is done faster, FFT also work faster. The working of various adders like ripple-carry adder, Sklansky adder, Kogge-Stone adder, and Brent-Kung adder is described in this thesis. By using these various adders working of FFT is also described in this thesis. The ripple-carry adder, Sklansky adder, Kogge-Stone adder, and Brent-Kung adder are implemented in Verilog using Cadence tools. By using these various adders, FFT using RCA, FFT using Sklansky adder, FFT using Kogge-Stone adder, and FFT using Brent-Kung adders are implemented in Verilog using Cadence tools. The performance of various FFT’s is compared in terms of cell count, power, and delay.
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Cite This Article

  • ISSN: 2349-6002
  • Volume: 11
  • Issue: 5
  • PageNo: 1282-1286

Exploring CMOS Technology for High-Speed and Efficient BCD Adder Designs

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Impact Factor
8.01 (Year 2024)
UGC Approved
Journal no 47859

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