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@article{183074,
        author = {Santhoshini P and Shirnidhi LK and Srinithi Bharathi V S and Thangaroja K and Theejha Aswini T and Bhavya sri V},
        title = {A Survey of Development of a Stable CMOS Amplifier Architecture for Diverse Capacitive Load Environments},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {12},
        number = {3},
        pages = {68-71},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=183074},
        abstract = {This paper presents the design and implementation of a fully differential two-stage CMOS amplifier that achieves unconditional stability for any capacitive load. Unlike traditional methods, this approach introduces a novel technique where a scaled replica of the output stage current is fed back to the amplifier’s virtual ground. This technique generates a left half-plane (LHP) zero in the loop gain, enabling dynamic pole-zero cancellation or tracking—ensuring consistent phase margin and stable frequency response, even under varying process, voltage, and temperature (PVT) conditions. Building on a previous gain-programmable amplifier designed using a 0.18 µm BCD (Bipolar-CMOS-DMOS) process—which was limited to driving loads up to 10 pF—we integrated a compact feedback block that significantly extends its capacitive drive capability without sacrificing stability. A frequency-domain analysis of the unloaded output impedance was also employed as an alternative method to validate the circuit’s robustness. Measurement results confirmed the design's performance under all tested load scenarios, while the added circuit required just 0.0004 mm² of chip area and consumed only 2 µA from a 5V supply.},
        keywords = {CMOS amplifier, capacitive load, LHP zero, loop gain, OTA, Miller compensation, unconditional stability.},
        month = {July},
        }