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@article{172429,
        author = {Santhoshini P and Vishwa R and Thangaselvam R and Vasanth P and Vineeth A},
        title = {Structural Testability  Data Analysis of Synchronous Sequential Circuits},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {8},
        pages = {3165-3171},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=172429},
        abstract = {Industries are increasingly focusing on sophisticated components for the development of multi-purpose machinery and devices, driven by the habitual integration of engineering and technology. Bounds on test sequence length can be used as a testability measure. We give a procedure to compute the upper bound on test sequence length for an arbitrary sequential circuit. We prove that the bound is exact for a certain class of circuits. Three design rules are specified to yield circuits with lower test sequence bounds.},
        keywords = {VLSI, Deep Learning, FPGA, Neural Networks.},
        month = {January},
        }