Optimization And Verification Of Bus Interface Unit (BIU) To Increase Performance Of The In-House Developed 32-Bit RISC Processor Core

  • Unique Paper ID: 102297
  • PageNo: 1591-1594
  • Abstract:
  • No Abstract Found

Copyright & License

Copyright © 2026 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

BibTeX

@article{102297,
        author = { Leema Rachel Mathew and Roopashree},
        title = { Optimization And Verification Of Bus Interface Unit (BIU) To Increase Performance Of The In-House Developed 32-Bit RISC Processor Core},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {1},
        number = {12},
        pages = {1591-1594},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=102297},
        abstract = {},
        keywords = {},
        month = {},
        }

Cite This Article

Mathew, L. R., & Roopashree, (). Optimization And Verification Of Bus Interface Unit (BIU) To Increase Performance Of The In-House Developed 32-Bit RISC Processor Core. International Journal of Innovative Research in Technology (IJIRT), 1(12), 1591–1594.

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