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@article{142364,
        author = {Liril George and R.H. Khade and Padmaja Bangde},
        title = {32 bit ALU using Clock Gating and Carry Select Adder},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {2},
        number = {1},
        pages = {205-210},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=142364},
        abstract = {ALU is a fundamental building block of CPU found in computer. It does all process related to arithmetic and logic operations. As the operations become more complex,the ALU become more complex, more expensive and takes up more space in the CPU hence power consumption is a major issue.In this paper, a 32 bit ALU is designed using VHDL. Lower power consumption is achieved using clock gating and the results are compared with 32 bit ALU without clock gating. A carry select adder is used for the arithmetic unit to perform fast arithmetic functions.The design is then implemented in Xilinx Spartan 3E FPGA},
        keywords = {ALU, Clock Gating, FPGA, Spartan 3E, FPGA, CMOS, VHDL},
        month = {},
        }