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@article{144191,
        author = {JOEL R and GNANA SARAVANAN S},
        title = {POWER AND STABILITY ANALYSIS OF 6T 7T SRAM CELL USING POWER GATING TECHNIQUES},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {3},
        number = {8},
        pages = {139-144},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=144191},
        abstract = {Low power memory is required today most priority with also high stability. The power is most important factor for today technology so the power reduction for one cell is vital role in memory design techniques.This paper is mainly focusing on reducing total power consumption of Static Random Access Memory (SRAM).A new seven transistor SRAM (7T) is proposed in this paper which eliminates the stability issues, reliable write and has a reduced cell area.  Leakage current in proposed 7T SRAM cell without Super cut-off word lines is almost same as in 6T SRAM cell and proposed 7T SRAM cell with super cut-off word lines is reduced by 26% of leakage power present in 6T SRAM cell. Compared to the conventional 7T  SRAM cell, the proposed cell has reduced write delay, read power consumption and write power consumption. Read delay is reduced by almost half of the standard 7T SRAM.  Leakage current in standby mode is the major part of power loss.Additionally this paper employ a new technique to reduce static power dissipation of conventional 6T, 7T SRAM cell using  low threshold voltage (Vth) transistor. The additional NMOS device is added between power supply and pull up device to apply reduced power supply (VDD) in standby mode and send maximum VDD in active mode to 6T SRAM cell. To do this, gate of extra NMOS is connected to word line of SRAM and substrate is biased to Vdd. The transient analysis for read, write and hold operations of conventional 6T, Proposed 7T SRAM are performed and static power dissipation, total power consumption is calculated using Tanner EDA tool. The proposed 7T SRAM is compared with existing 6T, 7T  SRAM cells in 45nm technology. The Overall performance of proposed 7T is better than existing 6T, 7T.  },
        keywords = {SRAM memory cell, Data Stability,  Leakage Power, static power dissipation, substrate,Low threshold voltage, NMOS, Threshold Voltage.},
        month = {},
        }