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@article{144532,
        author = {Bukya Balaji},
        title = {A Revision of On-Chip Interconnection Modeling for High Speed VLSI Systems},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {3},
        number = {1},
        pages = {392-396},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=144532},
        abstract = {This paper presents closed–form expressions for RC and RLC interconnection trees in current mode signaling, which can be employed in VLSI design tool. These investigative model expressions can be used for precise calculation of delay after the design clock tree has been located out and the design is fully routed.Assessment of these analytical models is several orders of magnitude faster than simulation using SPICE.
},
        keywords = {IC design, RC/RLC Interconnection, VLSI Systems},
        month = {},
        }