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@article{145320,
        author = {S.V.V.Sudhakar and R.Radha Kumari},
        title = {Novel Shared Multiplier Scheduling Scheme For Area-Efficient FFT/IFFT Processors},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {4},
        number = {9},
        pages = {24-31},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=145320},
        abstract = {This paper based on a new shared multiplier scheduling scheme (SMSS) for area-efficient fast Fourier transform (FFT)/inverse FFT processors. SMSS can significantly reduce the total number of complex multipliers up to 28%. The proposed mixed-radix multipath delay commutator processors can support128/256 and 256/512-point FFTs using SMSS. The proposed processors have been designed and implemented with 90-nm CMOS technology, which can reduce the total hardware complexity by 20%. The proposed processors having eight-parallel data paths can achieve a high throughput rate up to 27.5 GS/s at 430 MHz. In addition, the proposed processors can support any FFT size using additional stages},
        keywords = {Fast Fourier transform (FFT), mixed-radix multipath delay commutator (MRMDC)},
        month = {},
        }