Copyright © 2026 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

@article{146388,
        author = {S.PRASANNA DEVI and G.KAVITHA},
        title = {Radix-2 FFT Bit Reversal Architecture to Process double Data Streams for MIMO},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {4},
        number = {12},
        pages = {524-534},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=146388},
        abstract = {Bit-reversal is an essential part of the fast Fourier transform. However, compared to the amount of works on FFT architectures, much fewer works are dedicated to bit-reversal circuits until recent years. In this brief, the minimum latency and memory required for calculating the bit-reversal of continuous-flow parallel data are formulated. The proposed circuit is simple and efficient for reordering the output samples of parallel pipelined FFT processors. The proposed approach can be Implemented using Verilog HDL and Simulated by Modelsim 6.4 c. Finally it‟s synthesized by Xilinx tool.},
        keywords = {Bit-reversal circuit, fast Fourier transform (FFT), MDC, MDF, natural-order FFT output.},
        month = {},
        }