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@article{146637,
        author = {R.RAMESH NAIK and S.SAIDARAO},
        title = {A VLSI DESIGN OF LTE TURBO ENCODER-DECODER WITH RADIX 4 ACS ARCHITECTURE},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {5},
        number = {1},
        pages = {287-291},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=146637},
        abstract = {Wireless communication is the fastest developing portion of the communications industry. Channel coding is the most important part of digital wireless communication systems. The fading of signal due to multipath propagation causes errors which need to be corrected. The main aim of any channel coding schemes is to provide error-free data transmission by adding redundancy to information to check code and correct errors. Forward error correction (FEC) is favored strait coding procedure if the most extreme permitted transference delay is small or during the returning strait is not accessible. One imperative category of forward error correction codes are turbo codes. Turbo codes accomplish greater coding benefit and foremost utilized for error emendation in high rate wireless frameworks. This paper depicts a turbo decoder for Long Term Evolution (LTE) standard, utilizing a MAP algorithm. Long-term evolution (LTE) is expected to accomplish maximum information assess in surplus of 300 Mbps for fourth era wireless transferral networks. Turbo codes predetermined strait coding plan in LTE, experiences small decoding throughput because of frequentative decoding calculation. An effective way to accomplish favourable throughput is to utilize maximum a posteriori (MAP) basics in equidistant.},
        keywords = {},
        month = {},
        }