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@article{147517,
        author = {Faraaz Ansar Siddiqui and Vaishnavi Joglekar  and Somiya Pathan and Sunidhi Bopte and Rahil Khan},
        title = {A Review on High Performance Architecture for Packet Classification for Secure Communication Network},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {5},
        number = {8},
        pages = {208-211},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=147517},
        abstract = {Packet Classification is a core function used in an internet router, firewall, network security and quality of services. Packet classification technique is very crucial since various unauthorized and malicious networks are being exposed to. For secure networking and avoiding unauthorized access, incoming packets flow based on predefined rules available in a classifier. Available software solution’s performance is not efficient for wire speed processing in high speed networks. To meet the line-card requirement and wire speed processing hardware solution is more efficient and secure than software solution. For implementing hardware architecture for wire speed processing different algorithms have been proposed. This paper presents review on different algorithm and technique used to implement packet classification architecture. High performance packet classification architecture can be implemented using Field programmable gate array (FPGA) and large number of rules can be stored using on-chip memory resource of FPGA.},
        keywords = {Packet classification, 5-tuple, Quality of services, latency, throughput.},
        month = {},
        }