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@article{154355,
        author = {K.Chandrika and K.Mamatha},
        title = {CNFET-BASED TERNARY LOGIC CIRCUITS},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {8},
        number = {11},
        pages = {255-263},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=154355},
        abstract = {In today's world, binary logic is implanted utilising CMOS. However, CMOS has a number of drawbacks, including high leakage power and short channel effects. CNFET is used to implement ternary logics to avoid these drawbacks. The main benefit of ternary logics is that they take up less space on the chip and need less memory. Half Adder circuit for ternary logic is proposed in this paper. To begin, a decoder is employed to convert ternary to binary signals. Following that, binary signals are processed using a binary Half Adder before being transformed to ternary using an Encoder. The disadvantage of utilising a basic encoder is that it has a low resistance route and so consumes a lot of power. To deal with this, different encoders are used, such as the basic encoder and the enhanced encoder. In order to save energy, Encoders with low power consumption are employed. To eliminate latency, high-speed encoders are used. Variables such as chirality, diameter, pitch, number of tubes, oxide thickness, and dielectric materials are used to perform a detailed analysis of the encoder's power consumption and delay. This optimised Encoder is used in conjunction with a Half Adder.},
        keywords = {CNFET, ternary logic, basic Encoder, enhanced, low power, high speed Encoder, Half Adder. },
        month = {},
        }