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@article{154712,
        author = {G. Venkata Rao and P. Vineela Sri Charani and SK. Rahaman and T. Sasank},
        title = {COMPARATIVE ANALYSIS OF NAND GATE AND D FLIP-FLOP IN TERMS OF DELAY AND POWER},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {8},
        number = {12},
        pages = {143-151},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=154712},
        abstract = {The NAND gate is the highest priority gate in VLSI industry and D Flip-Flop is the basic element in shift register. The NAND gate and D Flip-Flop are implemented in different technologies like CMOS (180nm, 90nm, 45nm) technology and FINFET (18nm) technology. This work compares NAND gate as well as D Flip-Flop in various technologies in terms of delay and power. The Cadence tool is the leader of VLSI industry. This Cadence tool is used to implement the NAND gate and D flip flop. The simulation results were performed through Cadence Virtuoso environment at temperature 27 °C. },
        keywords = {NAND, D Flip flop, CMOS, VLSI.},
        month = {},
        }