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@article{156065,
        author = {Ganavi V S and Dr. Rekha K R},
        title = {System Level Modeling using SystemC},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {9},
        number = {2},
        pages = {803-805},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=156065},
        abstract = {System level design and IP interchange are planned to be made possible via SystemC, a new modelling language based on C++. This paper first explains system level modelling features before quickly reviewing the hardware modelling features included in SystemC. In the SoC design flow, transaction level modelling (TLM) is suggested as a prospective improvement over register transfer level (RTL). In order to address SoC design processes such as early software development, architecture analysis, and functional verification, this article formalises TLM abstractions. The genuine hardware/software co-design is the most satisfying aspect of TLM. SystemC allows for modelling of systems above the RTL level of abstraction, including those that may be implemented in hardware, software, or a combination of the two. The new features make system level design activities easier, by connecting design specifications to hardware and software implementations, as shown by a simple design example.},
        keywords = {SystemC, Transaction Level Modelling, Register Implementation, Application of Registers},
        month = {},
        }