Copyright © 2025 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

@article{156811,
        author = {Akash.H.Deepak  and Vijayaprakash A.M},
        title = {Design of High Efficient Video Encoder H.265},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {9},
        number = {5},
        pages = {65-72},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=156811},
        abstract = {In this project, we have designed an efficient Motion Estimation (ME) processor or engine for High Efficiency Video Coding (HEVC) systems is presented, along with its algorithm and VLSI architecture.The Exhaustive Search Algorithm that is implemented in this project, in particular, dramatically reduces the number of search possibilities while customizing the search space to the characteristics of the video.According to the experimental findings, this algorithm reduces computational complexity by 54% compared to traditional methods with just a slight performance hit of 2.01%. Additionally, this article presents the suggested ME engine's VLSI design and circuit implementation. Illustrated are the system level and gate level optimizations for increasing efficiency and lowering complexity. },
        keywords = {H.265 Encoder, Verilog, FPGA, Xilinx,Genus},
        month = {},
        }