Optimized VLSI Architectures for Signal Processing and Data Compression: A Comparative Analysis

  • Unique Paper ID: 184707
  • Volume: 12
  • Issue: 4
  • PageNo: 2830-2835
  • Abstract:
  • The evolution of Very Large-Scale Integration (VLSI) architectures has significantly improved computational efficiency in signal processing, video compression, and data encoding. This paper reviews three innovative VLSI designs: Feedforward FFT hardware architectures, which enhance efficiency through optimized rotator allocation; HEVC deblocking filter architectures, which improve video compression performance; and high-speed Huffman encoder architectures, which maximize data encoding throughput. A comparative analysis of these architectures highlights their unique advantages, efficiency improvements, and potential future applications. The discussion explores hardware optimization techniques, computational trade-offs, and real-world implementation considerations.

Copyright & License

Copyright © 2025 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

BibTeX

@article{184707,
        author = {NIRANJAN SHETTAR and Santosh S Bujari},
        title = {Optimized VLSI Architectures for Signal Processing and Data Compression: A Comparative Analysis},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {12},
        number = {4},
        pages = {2830-2835},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=184707},
        abstract = {The evolution of Very Large-Scale Integration (VLSI) architectures has significantly improved computational efficiency in signal processing, video compression, and data encoding. This paper reviews three innovative VLSI designs: Feedforward FFT hardware architectures, which enhance efficiency through optimized rotator allocation; HEVC deblocking filter architectures, which improve video compression performance; and high-speed Huffman encoder architectures, which maximize data encoding throughput. A comparative analysis of these architectures highlights their unique advantages, efficiency improvements, and potential future applications. The discussion explores hardware optimization techniques, computational trade-offs, and real-world implementation considerations.},
        keywords = {Feedforward FFT, HEVC Deblocking Filter, Huffman Encoding, Parallel Processing, Memory Interlacing},
        month = {September},
        }

Cite This Article

  • ISSN: 2349-6002
  • Volume: 12
  • Issue: 4
  • PageNo: 2830-2835

Optimized VLSI Architectures for Signal Processing and Data Compression: A Comparative Analysis

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