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@article{169984,
        author = {Nirmala S O and Leela G H and G S Sunitha and Vanishree H V},
        title = {DESIGN & VERIFICATION OF SINGLE PRECISION FLOATING POINT ALU},
        journal = {International Journal of Innovative Research in Technology},
        year = {2024},
        volume = {11},
        number = {6},
        pages = {2679-2682},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=169984},
        abstract = {A single precision floating-point arithmetic logic unit (ALU) is considered as a part of the math coprocessor. Summation, Subtraction, multiplication and division are arithmetic functions in these calculations. In this floating-point unit, input must be provided in IEEE-754 format, which is 32-bit single precision floating point values. The application of this arithmetic unit is located in the math coprocessor. In a Reduced Instruction Set Computation (RISC) processor, for signal processing, a value with high accuracy is required and as it is an iterative process, the calculation should be as fast as possible. The floating-point representation can calculate very large or very small process quickly and accurately. The system will be designed, verified and implemented with Verilog hardware description language using Cadence software tool.},
        keywords = {floating point, IEEE-754, Single Precision, synthesis},
        month = {November},
        }