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@article{171094,
        author = {Chitaraj Karan and D S Jayanth and Harsh Raj Karan and Jagriti Tiwari and Dr M Roopa},
        title = {Design and Area verification of CMOS Two Stage OP-AMP in 45nm Technology},
        journal = {International Journal of Innovative Research in Technology},
        year = {2024},
        volume = {11},
        number = {7},
        pages = {2846-2849},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=171094},
        abstract = {The design and area verification of a two-stage operational amplifier (op-amp) that is designed for effective functioning in integrated circuits are the main goals of this research. High gain, stability, and low area consumption while following industrial norms are among the goals. Techniques include a thorough design approach that balances power, speed, and area limitations employing CMOS technology, Cadence simulation, and layout optimization. To guarantee the intended functionality, important parameters including gain, phase margin, and power dissipation are regularly monitored. The results show that the developed op-amp raises 58 dB with a 63 degree phase margin while taking up very little chip space, making it ideal for small and effective circuit designs. Analog signal processing, data converters, and low-power applications are among the uses, and there is potential for future improvements in scaling and integration for smaller technology nodes..},
        keywords = {Two-stage op-amp, CMOS design, gain stability, area optimization, analog circuits},
        month = {December},
        }