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@article{172888,
        author = {Pratiksha P Hosamani and Nikhil Kulkarni and Deepak Sharma},
        title = {Design and Simulation of 8-Bit Ripple Carry Adder using 45nm Technology},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {9},
        pages = {1754-1761},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=172888},
        abstract = {For the Modern Digital Systems the computational performance can be enhanced by an efficient Arithmetic unit. The proposed work describes about the design and implementation of the adder Architectures which are proposed in this work using XOR, AND, OR Logic and Second by NAND Logic with 45 nm CMOS technology. Adders play a crucial role in processors, digital signal processing, and various computational applications, making their optimization vital for performance improvement. The Ripple Carry Adder (RCA) is known for its simplicity and minimal area usage, as it generates the sum and carry sequentially. However, this architecture suffers from significant propagation delay, which increases linearly with the number of bits, making it less suitable for high-speed operations. The design utilizes CMOS logic gates optimized for minimal power consumption and delay reduction. Cadence Virtuoso with 45 nm process technology is utilized in the proposed work.},
        keywords = {Ripple Carry Adder (RCA),8-bit Ripple Carry Adder.},
        month = {February},
        }