Copyright © 2025 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

@article{172890,
        author = {Akshata M Hosamani and Suraj Kadli},
        title = {LOW POWER FLIP FLOP USING CADENCE},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {9},
        pages = {1749-1753},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=172890},
        abstract = {Power consumption is a critical concern in modern VLSI design, particularly in sequential circuits such as D flip-flops. This paper presents the design and simulation of a low-power D flip-flop using Cadence Virtuoso and Spectre simulator. Various design techniques, including clock gating, transistor sizing optimization, and conditional data mapping, are explored to achieve power efficiency. The proposed design demonstrates a significant reduction in power consumption compared to conventional D flipflops, making it suitable for low- power applications in VLSI circuits.},
        keywords = {},
        month = {February},
        }