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@article{174742,
        author = {Tejaswini T and Tarun S N and Manjunath Umesh Kudalagi and Dr. Govinda Raju M},
        title = {Heterogeneous Computing Architectures in SoCs for 5G Communication},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {11},
        pages = {1739-1746},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=174742},
        abstract = {The advent of 5G communication systems has enormously raised the need for low-power, high-performance computing solutions that can manage massive data processing in real-time. Conventional homogeneous computing structures fail to cope with these needs because they lack adequate parallel processing capacity and high-power consumption. System-on- Chip (SoC) heterogeneous computing architectures provide a viable solution with multiple specialized processing blocks such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), Digital Signal Processors (DSPs), Field-Programmable Gate Arrays (FPGAs), and Application-Specific Integrated Cir- cuits (ASICs). Heterogeneous architectures allow for optimized task allocation, boosting computational performance, power man- agement, and scalability for 5G functions like signal processing, beamforming, channel estimation, and error correction. Never- theless, hurdles like software complexity, memory management, interconnect overhead, and thermal issues have to be dealt with to enable the complete promise of heterogeneous SoCs in 5G. This paper discusses design methodologies, optimization strategies, and future directions of heterogeneous computing architecture, emphasizing the pivotal role played by them in next-generation wireless communication.},
        keywords = {5G Communication, Heterogeneous Computing, SoCs, CPUs, GPUs, DSPs, FPGAs, ASICs, Parallelism, Energy Efficiency, Beamforming, Channel Estimation, Error Correction.},
        month = {April},
        }