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@article{176717,
        author = {B.C.Bhuvaneshwar and Dr.L.L.Prasanna Kumar and P. Raghu Ram Naidu and G. Vishnu Vardhan},
        title = {POWER EFFICIENT SYNCHRONOUS COUNTER DESIGN},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {11},
        pages = {7520-7523},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=176717},
        abstract = {The performance of VLSI circuits hinges on their design architecture, focusing on optimizing power usage and enhancing reliability. Achieving low power consumption necessitates power optimization across various circuit levels. Many system-level architectures incorporate sequential circuits, whose design significantly influences the overall system power. Counters, fundamental components in VLSI applications like timers, memories, and ADCs/DACs, often introduce power inefficiencies due to high clock signal power requirements and unintended flip-flop activities. This brief introduces a power-efficient design for synchronous counters, minimizing clock-related power consumption and improving reliability. Evaluated using standard 180 nm CMOS technology in CADENCE, our design outperforms current counter architectures in both power demand and power-area product, especially benefiting wide-bit counters.},
        keywords = {VLSI design, synchronous counters, clock gating, power efficiency, CMOS technology, CADENCE.},
        month = {April},
        }