POWER EFFICIENT SYNCHRONOUS COUNTER DESIGN

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B.C.Bhuvaneshwar; Dr.L.L.Prasanna Kumar; P. Raghu Ram Naidu; G. Vishnu Vardhan

POWER EFFICIENT SYNCHRONOUS COUNTER DESIGN

Authors: B.C.Bhuvaneshwar, Dr.L.L.Prasanna Kumar, P. Raghu Ram Naidu, G. Vishnu Vardhan

Unique Paper ID: 176717
Volume: 11
Issue: 11
PageNo: 7520-7523

Keywords: VLSI design synchronous counters clock gating power efficiency CMOS technology CADENCE.

Abstract:
The performance of VLSI circuits hinges on their design architecture, focusing on optimizing power usage and enhancing reliability. Achieving low power consumption necessitates power optimization across various circuit levels. Many system-level architectures incorporate sequential circuits, whose design significantly influences the overall system power. Counters, fundamental components in VLSI applications like timers, memories, and ADCs/DACs, often introduce power inefficiencies due to high clock signal power requirements and unintended flip-flop activities. This brief introduces a power-efficient design for synchronous counters, minimizing clock-related power consumption and improving reliability. Evaluated using standard 180 nm CMOS technology in CADENCE, our design outperforms current counter architectures in both power demand and power-area product, especially benefiting wide-bit counters.

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Cite This Article

ISSN: 2349-6002
Volume: 11
Issue: 11
PageNo: 7520-7523

POWER EFFICIENT SYNCHRONOUS COUNTER DESIGN

Available:https://ijirt.org/article?manuscript=176717

Impact Factor
8.01 (Year 2024)

UGC Approved
Journal no 47859

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