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@article{176756,
        author = {M. Surekha and M. Divya Gowthami and M. Srikanth Reddy and M. VenuMadhav},
        title = {An Ultra Efficient Approximate Multiplier for Error Resilient Applications},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {11},
        pages = {6307-6311},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=176756},
        abstract = {This paper presents a novel approximate multiplier architecture tailored for error-resilient applications such as image processing and machine learning. The proposed design emphasizes reduced hardware complexity, high operational speed, and improved area efficiency without compromising acceptable accuracy. By optimizing the partial product generation and employing segment-based approximate addition, the multiplier significantly reduces critical path delay and resource utilization. The design achieves high performance in applications where slight computational inaccuracies are tolerable, making it suitable for next-generation edge and embedded systems.},
        keywords = {Approximate computing, error-tolerant arithmetic, area-efficient design, high-speed multiplier, hardware simplification.},
        month = {April},
        }