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@article{178243,
        author = {Mrs.RNS.KALPANA and KADARI ARUN KUMAR and DESHABOINA HEMAVATHI and DODLA ASHWITHA},
        title = {IMPLEMENTATION OF HIGH-SPEED: HIGH-SPEED 16BIT CARRY LOOK A HEAD ADDER USING 4BIT CLA ADDERS},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {12},
        pages = {4075-4078},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=178243},
        abstract = {In the realm of digital systems, the speed of arithmetic operations plays a crucial role in determining overall system performance. Among these operations, binary addition is the most fundamental and widely used. This paper presents the design and implementation of a high-speed 16-bit Carry Look ahead Adder (CLA) using modular 4-bit CLA blocks, optimized with CMOS technology. By segmenting the 16-bit adder into smaller 4-bit units, the design effectively reduces the carry propagation delay, which traditionally limits the speed of ripple carry adders. The CLA architecture exploits generate and propagate signals to predict carry values in advance, significantly enhancing computation speed. Implementing this architecture with CMOS ensures reduced power consumption, improved noise immunity, and enhanced performance. Simulation results demonstrate that the proposed 16-bit CLA design achieves notable improvements in speed and efficiency compared to conventional adder architectures, making it suitable for high-performance digital systems.},
        keywords = {},
        month = {May},
        }