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@article{199562,
        author = {Mrs.R.N.S.kalpana and P.VAMSI and K.KEERTHAN and MOHAMMAD MUJTABA and M.YOGA YASHWANTH},
        title = {Design and implementaion of a power-efficient synchronous Dual port memory using synthesis-based clock gating and pipelingd},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {12817-12821},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=199562},
        abstract = {This paper presents the design and implementation of a power-efficient synchronous dual-port memory using pipelined architecture and synthesis-based clock gating techniques. Conventional dual-port memory designs often result in high power consumption due to unnecessary switching activity and continuous clock operation. To overcome these limitations, the proposed design uses enable-controlled clock gating and optimized pipelined data transfer, thereby reducing dynamic power and improving efficiency. The architecture supports simultaneous read and write operations with effective conflict handling using priority-based access control. The memory is modeled using Verilog HDL and implemented using FPGA design tools such as Xilinx Vivado.},
        keywords = {Dual-Port RAM, Clock Gating, Pipelining, Verilog HDL, FPGA, Vivado, Low-Power Design.},
        month = {April},
        }