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@article{178570,
        author = {G.ANITHA CHOWDHARY and ERATI VIJAYA and K.HEMANTH REDDY and KALWA NEHA REDDY},
        title = {16-BIT VEDIC MULTIPLIER USING CARRY SKIP ADDER},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {12},
        pages = {3807-3810},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=178570},
        abstract = {In modern digital signal processing and computing applications, high-speed and low-power multiplication units are crucial for efficient performance. This paper presents the design and implementation of a 16-bit Vedic multiplier using a Carry-Skip Adder (CSA) to boost computational speed while maintaining efficient power. [1-5]The Vedic multiplier is based on ancient Indian Vedic mathematics, specifically the “Urdhva Tiryakbhayam (Vertically and Crosswise) Sutra”, which enables parallel processing of partial products, reducing latency (delay) compared to traditional multipliers.[11-18] The incorporation of the Carry-Skip Adder further optimizes performance by minimizing carry propagation delay, directing to faster addition of partial products. Simulation results demonstrate significant improvements in speed and power consumption compared to traditional multipliers such as the Array Multiplier and Booth Multiplier [19-21]. This technique is suitable for high-performance computing applications, including DSP, cryptography, and image processing [7-14].},
        keywords = {Vedic Multiplier, Carry Save Adder, Carry Skip Adder, Xilinx ISE 14.7 version},
        month = {May},
        }