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@article{179684,
        author = {Kankana Majumder and Foram Ka. Patel and Chintankumar S Patel and Anita N Bhatt},
        title = {DESIGN AND IMPLEMENTATION OF 6T SRAM USING CADENCE},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {12},
        pages = {8752-8756},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=179684},
        abstract = {This project presents the design and implementation of a Static Random-Access Memory (SRAM) system using the Cadence Virtuoso. SRAM is a key component in modern digital systems, particularly in cache memory, due to its high speed, low latency, and low static power consumption. The 6T SRAM cell is composed of two cross-coupled CMOS inverters forming a bistable latch and two access transistors that enable read and write operations through word and bit lines. In addition to the SRAM cell, essential peripheral circuits such as the sense amplifier and the pre-charge and equalizer circuits were also designed to ensure proper read and write operations.  
The design flow includes schematic design and functional verification using DC and transient analysis to evaluate the performance and stability of the circuits. The project successfully demonstrates the key aspects of SRAM design at the schematic level, highlighting the role of supporting circuits in enhancing memory reliability and operations.},
        keywords = {SRAM, CMOS, WL, BL, BLbar, Q, Qb},
        month = {May},
        }