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@article{185934,
        author = {M.JYOSHNA and G MAHENDRA},
        title = {LOW POWER FAST ADDERS USING NEW XOR AND XNOR GATES},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {12},
        number = {5},
        pages = {3515-3520},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=185934},
        abstract = {Abstract—This paper presents the design and analysis of low power, high speed adders using newly proposed XOR and XNOR gates. The performance of arithmetic circuits largely depends on the efficiency of XOR and XNOR gates used in sum and carry generation. The proposed XOR/XNOR circuits are designed using a hybrid CMOS logic style that combines transmission gate logic and pass transistor logic to minimize power consumption, propagation delay, and transistor count. These optimized XOR/XNOR gates are then integrated into different adder architectures such as Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA), and Carry Select Adder (CSLA). Simulation results, carried out using 90nm CMOS technology in Cadence Virtuoso, show that the proposed designs achieve significant improvements in terms of power, delay, and Power Delay Product (PDP) when compared to conventional CMOS adder implementations. Hence, the proposed low power fast adders using new XOR and XNOR gates are highly suitable for low voltage and high-performance VLSI applications.},
        keywords = {Low power design, Fast adders, XOR gate, XNOR gate, Hybrid logic, Ripple carry adder, carry look ahead adder, Carry select adder, CMOS VLSI, Power delay product, Transmission gate logic, Pass transistor logic},
        month = {October},
        }